Photoresist is a light-sensitive material used in photolithography to form a patterned layer on a surface. In a positive resist, the portion of the photoresist that is exposed to light becomes soluble to a photoresist developer. The portion of the photoresist that is unexposed remains insoluble to the photoresist developer. In a negative resist, the portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer. The portion of the photoresist that is unexposed is dissolved by the photoresist developer. The light used for developing photoresist includes ultraviolet (UV) or deep UV (DUV) light, wherein shorter wavelengths allow an increased resolution and hence a smaller minimum feature size to be achieved. The patterned photoresist is used to synthesize structures in or on the underlying semiconductor layer. Thus, the fidelity of the patterned resist directly affects the resulting geometry of the underlying layer.
Light scattering from non-planar wafer topography substrates can cause light exposure in photoresist areas normally unexposed. FIG. 10 illustrates an exemplary substrate 51 including a plurality of non-planar topographic features. These features include a shallow trench isolation (STI) area 52A and a polysilicon feature 54A, each of which can reflect light at different angles and affect the exposure of a desired patterned resist feature 53A. This scattered light tends to cause disruptions in pattern fidelity of the photoresist. These disruptions are called wafer substrate topography proximity effects (TPE) in the industry. For example, in the case of patterned resist 53A, the scattered light from STI 52A and polysilicon features 54A may result in a different critical dimension (CD) at the bottom than at the top. This CD variation may undesirably affect the CD transferred to the underlying area during a subsequent process step.
Note that state-of-the-art integrated circuit (IC) designs are increasingly complex. Therefore, dense patterns rather than sparse patterns are increasingly prevalent in IC designs. For dense patterns, the wafer topography sensitivity of the photoresist CD appears to be more pronounced compared to sparse patterns due to the scattering of light described above. Therefore, the TPE problem is expected to worsen as IC designs continue to evolve in complexity.
TPE has been ignored for 45 nm and larger node technologies due to its relatively small impact to pattern CDs. For smaller node technologies, bottom anti-reflective coatings (BARCs) have been used in conjunction with photoresists to mitigate TPE. However, for an implant layer patterning step, BARC is not a preferred solution due to increased implant process complexity. Therefore, for 32 nm and 28 nm node technologies, rule-based correction or model-based correction of TPE-induced CD variations can be used for the implant layer. However, for 20 nm node and below technologies, even more accurate TPE modeling becomes both desirable and necessary.
There are two simultaneously necessary but often contradictory requirements for any computational tools used to simulate TPE. One requirement is that the simulation of the photolithography process is accurate and reliable in predicting the final shape of developed photoresist. The other requirement is rapid execution of the simulation in order to make applications like model-based optical proximity correction and full-chip lithography rule checking practical. The phrase “fast simulation” is utilized herein to describe simulated photolithography effect processes when the second requirement is met (i.e., when full-chip model-based optical proximity correction and lithography rule checking can be completed within a few days).
Tools to simulate photolithography effects are currently available. For example, the Sentaurus™ lithography (S-Litho™) tool provided by Synopsys, Inc. can accurately simulate wafer substrate topography proximity effects by solving Maxwell's equations. As known by those skilled in the art, Maxwell's equations are a set of partial differential equations that, together with the Lorentz force law, provide the rudiments of accurately estimating optical effects, including photolithography. Unfortunately, this approach is computationally intensive, and therefore has long runtimes. As a result, this approach is not a fast simulator and is unsuitable for full-chip applications.
U.S. Pat. No. 8,719,736 entitled “Compact and accurate wafer topography proximity effect modeling for full chip simulation” (incorporated herein by reference in its entirety) discloses a methodology for composing a disturbance matrix from pre-computed T-matrices (i.e., transfer matrices). The T-matrices are generated for preselected layout descriptions by solving Maxwell's equations using rigorous computing techniques, which are impractical for fast simulation applications, and then the preselected layout descriptions and associated pre-computed T-matrices are stored in a library. During operation of the methodology proposed in the '736 patent, a disturbance matrix is generated for a selected circuit design region by dividing the circuit design region into component layout description pieces that are then matched with the preselected layout descriptions stored in the library, and the pre-computed T-matrices stored with the associated preselected layout descriptions are utilized to compute the disturbance matrix for the selected circuit design region. Mathematically, each disturbance matrix functions to calculate E-field disturbances caused by the particular optical properties of the structure materials (e.g., refraction index, absorption coefficient, etc.) forming a circuit design region in response to an incident E-field at a given incidence angle. These disturbance matrices are utilized, for example, in standard model-based mask correction tools that perform TPE correction by way of modeling incident light directed through a selected mask design and onto a photoresist layer. The disturbance matrices are used by the model-based mask correction tools to calculate light intensities at selected points in the photoresist layer caused by the underlying circuit design features, and then the calculated light intensities are used to detect regions experiencing problematic light intensities (e.g., regions where high light intensities produce undesirable photoresist development), and to provide mask design corrections designed to alleviate the problematic light intensity conditions. Although the T-Matrix library approach works well when the library contains layout descriptions that match all of the component layout description pieces, substantial delays are encountered with a suitable match cannot be found. Moreover, it is difficult to know ahead of time all layout descriptions that will be needed for a given circuit design, and it may be impractical to generate pre-computed T-matrices for all possible layout configurations.
What is needed is a method for calculating light intensity values generated in a photoresist layer during a model-based mask correction process that both qualifies for fast simulation and avoids the deficiencies of the prior art approaches set forth above. In particular, what is needed is a method for rapidly generating a disturbance matrix that can be used to accurately describe light intensity values inside a photoresist layer formed over an inhomogeneous substrate without the use of pre-computed T-matrices stored in a library.